搜索资源列表
cic_compiler_ds613
- 国外的CIC补偿滤波器设计文件，非常有用-Abroad, CIC compensation filter design files, very useful
ciccomp2
- 计算CIC补偿滤波器系数方法2 Matlab source code-another method of calculate CIC compensation filter coefficients
understanding_CIC_compensation_Filters
- 主要是讲CIC补偿滤波的设计与理解，里面有数学推导和程序实例，希望对大家有用-cic compensation filter design
cic_hb
- 用FPGA设计的cic和hb滤波器（积分疏状滤波器核半带滤波器）初学FPGA 的同学可以看一下啊-Using the FPGA design cic and hb filter (integral scanty shape filter nuclear half took filter)
comp_sheji1
- CIC补偿滤波器的VHDL代码。通常单级的CIC阻带衰减不够，级联后阻带衰减满足要求，但是通带衰减又太大，补偿滤波器就是为了满足带内衰减要求而设计的。-THE code of CIC compensation filter.
DDC_matlab
- 实现数字变下频的matlab程序，CIC,HB,FIR滤波器代码都在其中-Realize digital variable frequency under matlab, CIC, HB, FIR filter code in it
CIC_Decimator_2stages
- --Filename: gh_CIC_decimation_m1.vhd -- --Descr iption: --CIC Decimation Filter m = 1. -- --Copyright (c) 2005, 2006 by George Huber --an OpenCores.org Project --free to use, but see documentation for conditions -- -- Revision
cic3_decimator
- 积分梳状滤波器(CIC)设计，解释很清晰的，希望对大家有所启发-Integrator comb filter (CIC) design, explained very clearly, we hope to be inspired. ...
cic_core_latest.tar
- CIC Digital Filter Core
cic_core
- cic积分梳状滤波器的verilog代码-the cic integral comb filter verilog code
fir
- 积分梳状滤波器(CIC)设计；,有详细的步骤-Integrator comb filter ( CIC ) design
cic_decimator
- system generator 环境中构造cic数字滤波器 抽取-construct cic digital filter extraction system generator environment
cic_compensating
- CIC 补偿滤波器。采用两种方法来设计，一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。-CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab cod
cic_dec_8_three
- 用verilog语言实现一个3级、抽取率为2的8位hogenauer CIC抽取滤波器-Verilog language to achieve a 3, the extraction rate of 8 hogenauer CIC decimation filter
CIC_Compensation_Filter_Coefficients
- CIC补偿滤波器设计源代码，包含量化功能，可以作为FPGA开发滤波器设计数据。适用于CIC抽取和CIC插值滤波器的补偿滤波器应用。-CIC compensation filter design source code, including the quantization function can be used as a the FPGA development filter design data. Apply to CIC decimation filter compensation an
24CIC
- 基于fpga的抽取CIC滤波器设计,采用verilog编写，24抽取,仿真通过-Fpga-based CIC decimation filter design using verilog written, 24 extraction
CIC_filter_implement
- 实现CIC抽取滤波器，在多速率通信中经常需要用到的CIC抽取滤波器-CIC decimation filter implemented in the multi-rate communications often need to use the CIC decimation filter
CIC_4ORDER
- 4阶24倍抽取CIC滤波器的verilogHDL源代码，仿真测试代码及相关资料-4-order CIC decimation filter 24 times verilogHDL source code, simulation test code and related information
cic_cq
- 在altera平台用verilog硬件描述语言实现cic抽取滤波，包含完整的工程代码，已经仿真通过，可以直接用于实践-In the Altera platform using Verilog hardware descr iption language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
cic_cz
- 在altera平台用verilog硬件描述语言实现cic插值滤波，在modelsim软件中仿真通过，包含完整的工程代码，可以直接下载到FPGA中运行-In the Altera platform using Verilog hardware descr iption language CIC interpolation filter, through the simulation in Modelsim software, including the complete project co